Modeling Closed-loop Analog Matrix Computing Circuits with Interconnect Resistance
Mu Zhou (1), Junbin Long (2), Yubiao Luo (2), Zhong Sun (2 and 3) ((1) School of Electronics Engineering and Computer Science, Peking University, Beijing, China, (2) Institute for Artificial Intelligence, and School of Integrated Circuits, Peking University, Beijing, China, (3) Beijing Advanced Innovation Center for Integrated Circuits)
基于电阻随机存取存储器(RRAM)的模拟矩阵计算(AMC)电路显示出加速矩阵操作的强大潜力。 然而,随着矩阵尺寸的增长,互连电阻越来越多地降低计算精度并限制电路的可扩展性。 因此,对这些影响进行建模和评估对于制定有效的缓解战略至关重要。 传统的SPICE(带有集成电路强调的模拟程序)模拟器依赖于修改的节点分析,由于节点和反馈连接的二次增长,大型AMC电路变得异常缓慢。 在这项工作中,我们模拟了具有互连电阻的AMC电路,用于两个关键操作矩阵反转(INV)和特征向量计算(EGV),并提出了针对每个情况量身定制的快速求解算法。 这些算法利用了Jacobian矩阵的稀薄,从而实现了快速而准确的解决方案。 与SPICE相比,它们实现了几个数量级加速,同时保持高精度。 我们进一步扩展了开环矩阵向量乘法(MVM)电路的方法,展示了类似的效率增益。 最后,利用这些快速求解器,我们开发了一种基于偏置的补偿策略,可将 INV 的互连诱导错误减少 50% 以上,EGV 电路减少 70%。 它还揭示了相对于矩阵大小和互连电阻的最佳偏置的缩放行为。
Analog matrix computing (AMC) circuits based on resistive random-access memory (RRAM) have shown strong potential for accelerating matrix operations. However, as matrix size grows, interconnect resistance increasingly degrades computational accuracy and limits circuit scalability. Modeling and evaluating these effects are therefore critical for developing effective mitigation strategies. Traditional SPICE (Simulation Program with Integrated Circuit Emphasis) simulators, which rely on modified no...